//------------------------------------------------------------
//  Filename: vga_backlight.v
//   
//  Author  : wlduan@gmail.com
//  Revise  : 2017-08-21 18:01
//  Description: 
//   
//  Copyright (C) 2014, YRBD, Inc. 					      
//  All Rights Reserved.                                       
//-------------------------------------------------------------
//
`timescale 1ns/1ps
 
module VGA_BACKLIGHT ( 
    input clk_vga,  
    input rst,  

    input  wire [7:0]  backlight_pwm_ctnr,
    output reg         backlight_pwm
);  
wire clk = clk_vga;    
//--------------------------------------------------------
reg[7:0] cur_pwm_ctnr;
//--------------------------------------------------------
always @(posedge clk,posedge rst) begin
    if(rst)begin 
        cur_pwm_ctnr <= 8'b0;    
    end 
    else begin 
        cur_pwm_ctnr <= backlight_pwm_ctnr;
    end 
end 
//--------------------------------------------------------
reg[31:0] clk10khz_ctnr;
//--------------------------------------------------------
always @(posedge clk,posedge rst) begin
    if(rst)begin 
        clk10khz_ctnr <= 32'b0;    
    end 
    else begin 
        clk10khz_ctnr <= (clk10khz_ctnr < 2500)? (clk10khz_ctnr + 1) : 32'b0;
    end 
end 
//--------------------------------------------------------
reg[7:0] pwm_duty;
//--------------------------------------------------------
always @(posedge clk,posedge rst) begin
    if(rst)begin 
        pwm_duty <= 8'b0;        
    end 
    else if(clk10khz_ctnr == 2500)begin 
        pwm_duty <= (pwm_duty < 100)?(pwm_duty + 8'b1):8'b0;        
    end 
end 
//--------------------------------------------------------
always @(posedge clk,posedge rst) begin
    if(rst)begin 
        backlight_pwm <= 1'b0;        
    end 
    else begin 
        backlight_pwm <= (cur_pwm_ctnr > pwm_duty)?1'b1:1'b0;        
    end 
end 

endmodule
